Cadence Maestro puts domain-trained AI agents to work for chip design

Artificial intelligence has been part of semiconductor design for years, helping engineers optimize chip architectures for performance, power efficiency, silicon area and faster development. More recently, the industry has begun integrating large language models and AI agents into established electronic design automation (EDA) workflows. Now Cadence Design Systems is taking that approach further with its Maestro AI Model Portfolio, a collection of domain-specialized models designed to work with