Stacked-Die Multi-Chip Architectures: The Tradeoff Between Scaling And Power Delivery

By Kaladhar Radhakrishnan, Nicolas Butzen, and Vishal Javvaji The semiconductor industry has embraced multi-chip and stacked-die architectures as the primary path for continued performance scaling. As monolithic designs become more difficult and costly to advance, chiplets, advanced packaging, and 3D integration enable higher levels of performance, bandwidth, and functional integration for AI and high-performance computing (HPC) systems. Yet the success of stacked-die, multi-chip architectures h