How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å

As their dimensions continue to shrink, conventional gate-all-around (GAA) nanosheet transistors may face growing challenges, such as leakage, mobility, resistance, and manufacturing variability. A proposed self-aligned complementary field-effect transistor (SA-CFET) architecture addresses these constraints by vertically stacking N-channel metal-oxide-semiconductor (NMOS) and P-channel metal-oxide-semiconductor (PMOS) devices and using self-aligned modules to improve density and manufacturabilit