Accelerating Manufacturing-Aware Simulations For Photonic Integrated Circuits With FTCO And Digital Twins

Photonic integrated circuit (PIC) performance is increasingly bounded by fabrication realities such as sidewall angle, critical-dimension bias, thickness variation, and line-edge roughness, which idealized, as-drawn FDTD simulations fail to capture. Here, we show a Fab Technology Co-Optimization (FTCO) workflow that connects GDS layout import, three-dimensional process simulation, GPU-accelerated FDTD, design of experiments (DOE), with AI-based surrogate modeling. We show that when manufacturing