Strengthening Advanced-Node Interconnects Through Automated Via Insertion

As the semiconductor industry pushes deeper into the sub-5nm realm, the physical design landscape has shifted from being dominated by gate delays to being defined by interconnect performance. In modern system-on-chip (SoC) designs, the wiring that connects billions of transistors has become the primary bottleneck for power, performance, and area (PPA). Among the various components of the interconnect stack, vias – the vertical connections between metal layers – represent one of the most signific