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pulse Semiconductor Engineering September 28, 2026

Copper Grain Structure Influences Stress Around Scaled TSVs (Purdue, UCLA)

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Researchers at Purdue University and the UCLA published a technical paper titled “Experimental Evidence for the Impact of Copper Microstructure on Residual Stress of Through Silicon Via.” Abstract Excerpt: “Here, we experimentally quantify the impact of Cu microstructure on the TSV-induced residual stress within silicon. A 3-⁢m-diameter TSV array was annealed at 400 °C for 60 min, and the residual stress in the surrounding Si was imaged with Raman spectroscopy at room temperature. The Cu surface

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