Validating PCIe 6.0 Connectivity In A 3D Multi-Die Test Chip

AI, high-performance computing (HPC), data center switching, and storage systems are increasing the amount of data that must move across interfaces and between heterogeneous dies, or chiplets. That demand is exposing limits in traditional monolithic system-on-chip (SoC) architectures. Synopsys’ 3D PCIe 6.0 test-chip demonstration shows that 64.0 GT/s PCIe connectivity, with up to 128.0 GB/s delivered through an 8-lane configuration using PAM4 signaling, can be implemented and validated in a stac